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@a4lg a4lg commented Apr 30, 2025

This is the last batch (3 of 3) for RISC-V feature enhancements intended for the version 1.88 cycle.

The author's primary criteria are:

  1. The extension is ratified and unprivileged one.
  2. The extension is in the RVA23U64 profile (to be a baseline of the application-class RISC-V software ecosystem in the near future), either mandatory or optional.
  3. Either:
    1. To be discoverable through a riscv_hwprobe system call on (currently unreleased) Linux 6.15 (as of rc4) or
    2. Helps memory/atomics-related operations more efficient and/or more robust.

This is based on the specifications:

LLVM Definitions:

The Zicbop extension (mandatory in RVA23U64) adds prefetch hints to prepare for subsequent memory operations (will be executed as no-op if the hardware does not support this extension).

The Zicbom extension (mandatory in RVA23U64) adds cache block-management instructions. The author did not include this in the batch 2 (because of limited use cases compared to the Zicboz extension) but added because it will be discoverable from Linux (as of version 6.15-rc4). Along with Zicbop, Rust now supports all CMO extensions.

The Zic64b extension (mandatory in RVA23U64) constraints the cache block to be naturally-aligned and exactly 64 bytes. Along with CMO instructions, it can improve efficiency handling with memory (e.g. efficient memory zeroing using Zicboz + Zic64b).

The Zicc* extensions (mandatory in RVA23U64) add constraints to the main memory properties. They are normally satisfied in the application environment with regular OSes but profiles like RVA23U64 ensures such properties are satisfied (through those constraint extensions).

The Zfbf* and Zvfbf* extensions (optional in RVA23U64) add instructions to handle BF16 (BFloat16) data. Although stabilization of FP-related extensions are relatively far due to ABI-related issues, they are included in this batch because they will be discoverable from Linux (as of version 6.15-rc4).

The author also adds the extension implication: Za64rsZa128rs (superset) which the author missed to include in #140139.


Notes

  • Implication from Za64rs to Za128rs seem counterintuitive but they denote the maximum reservation set size as used in the LR/SC-based atomic operations. That means, smaller the reservation set is, more fine-grained control of atomics.

Related

History

Version 1 (2025-04-30)

The initial proposal.

Version 2 (2025-05-01)

Clarified that the feature implication of the Zfbfmin extension is not fully described in the source code (it also depends on load/store/move-(from/to)-GPR instructions from the Zfh extension or its subset: the Zfhmin extension) and needs extra care.

@rustbot r? @Amanieu
@rustbot label +T-compiler +O-riscv +A-target-feature

@rustbot rustbot added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. A-target-feature Area: Enabling/disabling target features like AVX, Neon, etc. O-riscv Target: RISC-V architecture labels Apr 30, 2025
a4lg added 3 commits May 1, 2025 00:09
The Za64rs extension (reservation set -- a primitive memory unit of LR/SC
atomic operations -- is naturally aligned and *at most* 64 bytes) is a
superset of the Za128rs extension (*at most* 128 bytes; note that smaller
the reservation set is, more fine grained control over atomics).

This commit handles this as a feature implication.
This commit adds a part of RISC-V extensions that are mandatory part of
the RVA23U64 profile (application-class processor profile) and related to
memory/atomic constraints.

The Zic64b extension constrains the cache line to naturally-aligned 64 bytes
that would make certain memory operations (like zeroing the memory using
the Zicboz extension) easier.

The Zicbom and Zicbop extensions enable managing cache block-based
operations (the Zicbop contains hints that will work as a NOP when this
extension is absent and the Zicbom contains control instructions).

Of which, the Zicbom extension is going to be discoverable from the Linux
kernel (as of the version 6.15-rc4) and this commit prepares for
corresponding stdarch changes.

The Zicc* extensions add certain constraints to "the main memory" (usually
true on the user mode application on the application-class processor but
those extensions make sure such constraints exist).
This commit adds three ratified unprivileged RISC-V extensions related to
BFloat16 (BF16) handling.

Although that they are far from stabilization due to ABI issues, they are
optional extensions of the RVA23U64 profile (application-class processor
profile) and going to be discoverable from the Linux kernel
(as of version 6.15-rc4).

This commit mainly prepares runtime detection of those extensions.
@a4lg a4lg force-pushed the riscv-feature-addition-batch-3 branch from 69d1db7 to 501a539 Compare May 1, 2025 00:14
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Amanieu commented May 1, 2025

@bors r+ rollup

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bors commented May 1, 2025

📌 Commit 501a539 has been approved by Amanieu

It is now in the queue for this repository.

@bors bors added S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels May 1, 2025
VlaDexa added a commit to VlaDexa/rust that referenced this pull request May 2, 2025
…3, r=Amanieu

rustc_target: RISC-V: feature addition batch 3

This is the last batch (3 of 3) for RISC-V feature enhancements intended for the version 1.88 cycle.

The author's primary criteria are:

1.  The extension is ratified and unprivileged one.
2.  The extension is in the RVA23U64 profile (to be a baseline of the application-class RISC-V software ecosystem in the near future), either mandatory or optional.
3.  Either:
    1.  To be discoverable through a `riscv_hwprobe` system call on (currently unreleased) Linux 6.15 (as of rc4) or
    2.  Helps memory/atomics-related operations more efficient and/or more robust.

This is based on the specifications:

*   [The latest ratified ISA Manuals (version 20240411)](https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications)
*   [RVA23/RVB23 profiles](https://github.com/riscv/riscv-profiles/releases/tag/rva23-rvb23-ratified)
*   [RISC-V BF16 extensions](https://github.com/riscv/riscv-bfloat16/releases/tag/v183a3dac863d7c18187a739eb52b0c8f0d16854d)

LLVM Definitions:

*   [`Zicbop`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L82-87)
*   [`Zicbom`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L75-L80)
*   [`Zic64b`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L71-L73)
*   [`Ziccamoa`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L97-L99)
*   [`Ziccif`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L101-L103)
*   [`Zicclsm`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L105-L107)
*   [`Ziccrse`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L109-L111)
*   [`Zfbfmin`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L320-L325)
*   [`Zvfbfmin`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L697-L702)
*   [`Zvfbfwma`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L704-L710)

The `Zicbop` extension (mandatory in RVA23U64) adds prefetch hints to prepare for subsequent memory operations (will be executed as no-op if the hardware does not support this extension).

The `Zicbom` extension (mandatory in RVA23U64) adds cache block-management instructions.  The author did not include this in the batch 2 (because of limited use cases compared to the `Zicboz` extension) but added because it will be discoverable from Linux (as of version 6.15-rc4).  Along with `Zicbop`, Rust now supports all CMO extensions.

The `Zic64b` extension (mandatory in RVA23U64) constraints the cache block to be naturally-aligned and exactly 64 bytes.  Along with CMO instructions, it can improve efficiency handling with memory (e.g. efficient memory zeroing using `Zicboz` + `Zic64b`).

The `Zicc*` extensions (mandatory in RVA23U64) add constraints to the main memory properties.  They are normally satisfied in the application environment with regular OSes but profiles like RVA23U64 ensures such properties are satisfied (through those *constraint* extensions).

The `Zfbf*` and `Zvfbf*` extensions (optional in RVA23U64) add instructions to handle BF16 (BFloat16) data.  Although stabilization of FP-related extensions are relatively far due to ABI-related issues, they are included in this batch because they will be discoverable from Linux (as of version 6.15-rc4).

The author also adds the extension implication: `Za64rs` → `Za128rs` (superset) which the author missed to include in rust-lang#140139.
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A-target-feature Area: Enabling/disabling target features like AVX, Neon, etc. O-riscv Target: RISC-V architecture S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
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