From b6b8ed48f98b5da7970459188497ae1844d02a43 Mon Sep 17 00:00:00 2001
From: tacsnac <29697830+tactical-snacks@users.noreply.github.com>
Date: Mon, 5 Jun 2023 22:31:43 -0400
Subject: [PATCH 1/6] enable avr-dd updi pin by default

---
 builder/fuses.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/builder/fuses.py b/builder/fuses.py
index edda251..d80188f 100644
--- a/builder/fuses.py
+++ b/builder/fuses.py
@@ -58,7 +58,8 @@ def get_syscfg0_fuse(eesave, pin, uart):
                 rstpin_bit = 1
         else:
             rstpin_bit = 1
-        return 0xC0 | rstpin_bit << 3 | eesave_bit
+        updipin_bit = 1 # handle AVR-DD updi pin
+        return 0xC0 | updipin_bit << 4 | rstpin_bit << 3 | eesave_bit
 
     elif core == "megatinycore":
         if pin == "gpio":

From 637b9756d7115e74276152c19d3b08a5a267c0e9 Mon Sep 17 00:00:00 2001
From: tacsnac <29697830+tactical-snacks@users.noreply.github.com>
Date: Mon, 5 Jun 2023 22:41:12 -0400
Subject: [PATCH 2/6] add mvio support for avr-dd

---
 builder/fuses.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/builder/fuses.py b/builder/fuses.py
index d80188f..2d74933 100644
--- a/builder/fuses.py
+++ b/builder/fuses.py
@@ -58,7 +58,7 @@ def get_syscfg0_fuse(eesave, pin, uart):
                 rstpin_bit = 1
         else:
             rstpin_bit = 1
-        updipin_bit = 1 # handle AVR-DD updi pin
+        updipin_bit = 1 # enable AVR-DD updi pin by default
         return 0xC0 | updipin_bit << 4 | rstpin_bit << 3 | eesave_bit
 
     elif core == "megatinycore":
@@ -74,9 +74,9 @@ def get_syscfg0_fuse(eesave, pin, uart):
     env.Exit(1)
 
 
-# Handle AVR-DB's differently since these has MVIO pins
+# Handle AVR-DB's and DD's differently since these has MVIO pins
 def get_syscfg1_fuse(mvio):
-    if core == "dxcore" and ("db" in board.get("build.mcu").lower()):
+    if core == "dxcore" and (("db" in board.get("build.mcu").lower()) or ("dd" in board.get("build.mcu").lower())):
         if(mvio == "yes"):
             return 0x0E
         else:

From 1d19f6d0db3788a5dfa86c6eef13f48ea8c688de Mon Sep 17 00:00:00 2001
From: tacsnac <29697830+tactical-snacks@users.noreply.github.com>
Date: Tue, 6 Jun 2023 14:27:38 -0400
Subject: [PATCH 3/6] not mess megacorex

---
 builder/fuses.py | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/builder/fuses.py b/builder/fuses.py
index 2d74933..e5ec94b 100644
--- a/builder/fuses.py
+++ b/builder/fuses.py
@@ -58,7 +58,10 @@ def get_syscfg0_fuse(eesave, pin, uart):
                 rstpin_bit = 1
         else:
             rstpin_bit = 1
-        updipin_bit = 1 # enable AVR-DD updi pin by default
+        if ("dd" in board.get("build.mcu").lower()):
+            updipin_bit = 1 # enable AVR-DD updi pin by default
+        else:
+            updipin_bit = 0            
         return 0xC0 | updipin_bit << 4 | rstpin_bit << 3 | eesave_bit
 
     elif core == "megatinycore":

From 89e21f5a1ff932ac9d9fa06592005365a008dbd2 Mon Sep 17 00:00:00 2001
From: tacsnac <29697830+tactical-snacks@users.noreply.github.com>
Date: Tue, 6 Jun 2023 14:33:25 -0400
Subject: [PATCH 4/6] mvio notify for avr-dd

---
 builder/fuses.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/builder/fuses.py b/builder/fuses.py
index e5ec94b..c3b90d0 100644
--- a/builder/fuses.py
+++ b/builder/fuses.py
@@ -156,7 +156,7 @@ def calculate_fuses(board_config, predefined_fuses):
     print("Oscillator = %s" % oscillator)
     print("BOD level = %s" % bod)
     print("Save EEPROM = %s" % eesave)
-    if core == "dxcore" and "db" in board.get("build.mcu").lower():
+    if core == "dxcore" and ("db" or "dd" in board.get("build.mcu").lower()):
         print("MVIO enable = %s" % mvio)
     print("%s = %s" % (
         "Reset pin mode" if core in ("MegaCoreX", "dxcore") else "UPDI pin mode", pin))

From 994f9155aed40fb43c01d5c168f73630a3e9ff23 Mon Sep 17 00:00:00 2001
From: tacsnac <29697830+tactical-snacks@users.noreply.github.com>
Date: Tue, 6 Jun 2023 14:38:58 -0400
Subject: [PATCH 5/6] clean up mvio fuse config

---
 builder/fuses.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/builder/fuses.py b/builder/fuses.py
index c3b90d0..8ec4cad 100644
--- a/builder/fuses.py
+++ b/builder/fuses.py
@@ -79,7 +79,7 @@ def get_syscfg0_fuse(eesave, pin, uart):
 
 # Handle AVR-DB's and DD's differently since these has MVIO pins
 def get_syscfg1_fuse(mvio):
-    if core == "dxcore" and (("db" in board.get("build.mcu").lower()) or ("dd" in board.get("build.mcu").lower())):
+    if core == "dxcore" and ("db" or "dd" in board.get("build.mcu").lower()):
         if(mvio == "yes"):
             return 0x0E
         else:

From c252bed3e107a45631e4b168e6d1f0659c44b6e4 Mon Sep 17 00:00:00 2001
From: tacsnac <29697830+tactical-snacks@users.noreply.github.com>
Date: Thu, 7 Sep 2023 21:50:31 -0400
Subject: [PATCH 6/6] allow updi pin as gpio

---
 builder/fuses.py | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/builder/fuses.py b/builder/fuses.py
index 8ec4cad..9eb7ca0 100644
--- a/builder/fuses.py
+++ b/builder/fuses.py
@@ -59,9 +59,12 @@ def get_syscfg0_fuse(eesave, pin, uart):
         else:
             rstpin_bit = 1
         if ("dd" in board.get("build.mcu").lower()):
-            updipin_bit = 1 # enable AVR-DD updi pin by default
+            if pin == "gpio":
+                updipin_bit = 0
+            else:
+                updipin_bit = 1
         else:
-            updipin_bit = 0            
+             updipin_bit = 0
         return 0xC0 | updipin_bit << 4 | rstpin_bit << 3 | eesave_bit
 
     elif core == "megatinycore":