tx_gen.py

# Processes four files representing the programming of the
# Tx data path, and emits Verilog for the corresponding program ROM.
# See tx_path.eps

from sys import argv
out_map = {'x': 'xx', 'pxd': '00', 'cfg': '01', 'tem': '10', 'chk': '11'}
chk_map = {'x': 'xx', 'pxd': '00', 'cfg': '01', 'tem': '10', '0': '11'}


def cvtbin(x, wid):
    if x == "x":
        return "x"*wid
    x = int(x)
    return "".join([str((x >> y) & 1) for y in range(wid-1, -1, -1)])


def convert(a, offset):
    entry = int(a[0]) + offset
    c1 = out_map[a[1]]
    c2 = cvtbin(a[2], 6)
    c3 = cvtbin(a[3], 6)
    c4 = chk_map[a[4]]
    c5 = cvtbin(a[5], 8)
    printme = entry, c1, c2, c3, c4, c5
    return "%8d: r = 24'b%s_%s_%s_%s_%s;" % printme


# pc out fp_offset cf_offset chk_in template comment
# -   2     5          5        2      8        -
def file_grab(fname, offset):
    with open(fname, 'r') as f:
        for ll in f.read().split('\n'):
            if ll == "" or ll[0] == "#":
                continue
            a = ll.split()
            if len(a) < 6:
                continue
            print(convert(a, offset))


print('''// Table lookup controlling output packet data path
// Machine-generated by tx_gen.py
// v = {out, fp_offset, cf_offset, chk_in, template};
module construct_tx_table(
    input [7:0] a,
    output [23:0] v
);
reg [23:0] r;  // really combinational
always @(*) case (a)''')
file_grab(argv[1], 0)
file_grab(argv[2], 64)
file_grab(argv[3], 128)
file_grab(argv[4], 192)
print(''' default: r = 24'b00_000000_xxxxxx_xx_xxxxxxxx;
endcase
assign v = r;
endmodule''')